Logic Design Intern

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About the job

Job Description

The Group: Intel's Advanced Design (AD) team resides within the Design Enablement (DE) organization, which collaborates closely with our partners in process technology, IP, and products spanning client/server and networking products. The primary focus of AD is to guide process technology definition, and design prototypes in Intel's latest process technology, supporting Intel's internal and external design customers.

The future of Moore's Law: 3D-IC

https://www.intel.com/content/www/us/en/newsroom/opinion/moore-law-now-and-in-the-future.html

https://www.zdnet.com/paid-content/article/moores-law-under-the-microscope-intel-advances-transistor-technology/

https://www.tomshardware.com/news/intel-teases-falcon-shores-xpu

The Role: The Design Technology Pathfinding (DTP) organization in Design Enabling (DE) is chartered to identify and drive key strategic initiatives in the pathfinding of future technologies, as a holistic Design co-optimization across the Product stack from System architecture to silicon as we extend DTCO to STCO (System Technology Co-Optimization). The job requires partnering and leveraging domain experts across Intel and the EDA Eco-System

Deliverables

• RTL and Logic Design and Pre Silicon Verification of Complex Hardware Systems.
• Analysis and Validation of IPs and SOCs, Memory, various protocols like AXI, JTAG, PCIE, Ethernet, or other complex ASIC, die-to-die designs.
• Create testcases in UVM and run pre-silicon verification tools.

Candidate must have communication skills, and a team player with ability to work independently in a fast-paced team and environment.

This is an internship for at least 6 months.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

Candidate must be pursuing a Ph.D. degree in Electrical Engineering or Computer Engineering with 1+ year of experience the following: